1. Field of the Invention
The present invention provides a method to evaluate a circuitry cross-talk during the practical operation of a circuit for the matching between the analysis result and the cross-talk on each wire in the circuit.
2. Description of the Prior Art
In the highly developed modern information society, an electric circuit used in signal processing and data calculation is the most vital fundamental part of information development. From portable cellular phones, personal digital assistants (PDA), to desktop computers, and network servers, different system demands for electric signal processing and information integration are fulfilled by complex electric circuits. The principal part of modern electric circuits is an integrated circuit manufactured in a wafer manufacturing process. An integrated circuit will be packaged in a chip to be applied in a semiconductor system.
With the advancements of wafer manufacturing processing, circuit layout size of an electric circuit gradually scales down and components integration will increase such that the chip volume will be decreased to further fulfill the demands of a tiny circuit of modern information society. However, as circuit volume is getting much smaller, distance between each component and wires becomes much less, signals transmitted in wires will interrupt each other because of mutual electric coupling effects, and communication quality will deteriorate. Signal interference between wires in a circuit because of mutual electric coupling effects is so-called “cross-talk” effect. To further explain the cause of cross-talk, please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional circuit 10. In circuit 10, circuit blocks 12A, 12B, 14A, 14B, 16A, 16B, 18A, and 18B are the construct components of circuit 10; each illustrated block represents a plurality of organized logic gates or transistors for performing specified function. Wires L1 to L4 in circuit 10 connect blocks 12A to 12B, 14A to 14B, 16A to 16B, and 18A to 18B, respectively with functions of transmitting electric signals between each electric circuit block.
Since circuit 10 has dense component integration distance between each wire will be very small, such as distance D12 and D23 illustrated in FIG. 1. In present 0.18 μm (micron) wafer manufacturing processing, distance between each wire could be less than 1 μm wherein mutual electric coupling effects between each wire will increase. Although in circuit 10 the wires L1, L2, L3, and L3 are insulated from each other, between each wire, a capacitor will be formed in an equivalent circuit, which makes wires couple mutually via this equivalent capacitor. As illustrated in FIG. 1, mutual electric coupling effects between L1 and L2 could be represented as an equivalent capacitor C12. Signals transmitted in L1 and L2 will interrupt each other via this equivalent capacitor C12 because of cross-talk effect. The mutual electric coupling effects between L2 and L3 could also be represented as an equivalent capacitor C23 and the mutual electric coupling effect between L4 and L1, L2, and L3 could be represented as a capacitor C14, C24, and C34, respectively. Among them, L1 is much closer to L2, which means that D12 is less than D23, and the parallel portion between L1 and L2 is longer, which means that D0 is longer. This means that the mutual electric coupling effects between L1 and L2 is much larger than that between others.
In order to further explain the effects of mutual electric coupling on a circuit, please refer to FIG. 2A and FIG. 1. FIG. 2A is a time sequence of signals transmitted in different wires. The horizontal axis represents time scale and the vertical axis represents signal potential scale. In an ideal situation, a good electric insulation exists between each wire in circuit 10 and signals transmitted in different wires will not interrupt each other. Wave patterns 20A and 20B illustrated in FIG. 2A represent digital signals transmitted in two different wires, such as L1 and L2 for example, in such an ideal situation. However, in reality, the mutual electric coupling effects between different wires will make signals of two wires interrupt each other and result in cross-talk. The wave pattern 20C illustrated in FIG. 2A represents the real wave pattern of wave pattern 20A, which is influenced by mutual electric coupling effects in circuit 10. From time point t0 to t1, the wave pattern 20A in the wire L1 shall maintain at low potential, but the wave pattern 20B in wire L2 is at high potential in the same time span, which prevents the wave pattern 20A from maintaining its low potential through the mutual electric coupling effects between wires and results in the wave pattern 20C having a slightly increased potential. Similarly, in the period time t1 to t2, the wave pattern of the signal transmitted in L1 shall maintain its high potential such as 20A, but low potential wave pattern 20B in L2 makes the wave pattern of L1 lower its potential through mutual electric coupling effects to become the wave pattern 20C. When the ideal wave pattern 20A in L1 degrades due to the wave pattern 20B, noise margin of the signal in L1 will decrease. As the wave pattern illustrated from time point t0 to t2 in FIG. 2A, there is a potential transition V0 in the ideal wave pattern 20A, but potential transition V1 in the wave pattern 20B is less than V0. If the potential transition V1 is too small or noise is too large, it cannot be determined whether the digital signal is at its high level or low level. Besides, at time point t3, both the wave pattern of L1 and L2 increase to a high potential level, and the wave pattern in L1 will exceed the normal potential level to a much higher level through the mutual electric coupling effects between wires, such as wave pattern 20C, which may result in burning out of the wire L1 for its forcing signal.
Cross-talk effects influence not only signal potential mentioned above, but also time domain expression. Please refer to FIG. 2B. Illustrated in FIG. 2B are time sequence representing different locations in wire L1 and L2. The horizontal axis represents time and the vertical axis represents signal potential. The electric block 12A should transmit signals to the electric block 12B through the wire L1, the electric block 14B should transmit signals to the electric block 14A through the wire L2, the wave pattern 26A, 26B, and 26C represent the wave patterns having potential transitions in locations 22A, 22B and 22C of the wire L2 and the wave pattern 28A, 28B, and 28C represent the wave patterns having potential transitions in locations 24A, 24B and 24C of the wire L2. As illustrated in FIG. 2B, wave pattern 26B has its rising edge at time point t5 and t6, but wave pattern 28B has its falling edge at the same time points. The falling edge of the wave pattern 28B will lower the rising velocity of the rising edge of the wave pattern 26B through mutual electric coupling, which results in a longer time needed for the wave pattern 26B to rise, and influences the potential transition speed of the wave pattern 26C. In other words, unexpected delays will occur in signals transmitted in the wire L1 for a rising edge and a falling edge occurring at the same time in different wires, and each electric block in circuit 10 will not operate concisely according to its default time domain.
Please refer to FIG. 3. In order to decrease cross-talk effects in a circuit due to mutual electric coupling, cross-talk effects of a circuit shall be analyzed specifically during electric circuit design process. FIG. 3 is a schematic diagram of a prior art flow 100 for analyzing cross-talk effects during electric circuit design. The flow 100 is as follows:
Step 102: Circuit Functions Design. According to function demands, needed electric components, such as transistors, or logic gates will be assigned in this step. In other words, in this step transistors or logic gates will be chosen to fulfill the demand for functions of a circuit. In FIG. 1, flow 100 will perform electric circuit design and cross-talk analysis for circuit 10. Circuit 10 is provided with functions of receiving signals A and B in electric circuit blocks 12A and 12B, applying an “AND” operation on signals A and B, inverting the resulting signal and outputting it as signal C; receiving a signal in electric circuit blocks 16A and 16B, buffering and outputting it as signal G with high driving capacity; and receiving a signal H in electric circuit blocks 18a and 18B, inverting the resulting signal and outputting it as signal I. Therefore, as illustrated in an attached graph in FIG. 3, components such as AND gate 30A and inverter 30B will be chosen to achieve the above-mentioned functions in this step.
Step 104: Circuit Layout Design. After determining the component assignment in circuit 10, how to practice the circuit design determined in step 102 with circuit layouts in real wafer manufacturing processing will be considered in this step. To a person having ordinary skills in the art, in wafer manufacturing processing, a doped region (active region), oxide layer, field oxide layer, conductive layer, and polysilicon layer will be applied to layouts of transistors, logic gates, or other components. In this step, square measure of each transistor and logic gate in different layers, layout layer between each transistor and logic gate (use a conductive layer to practice the wire L1 to L3, and another conductive layer to practice the wire LA for example) and the layout width and length illustrated in the attached graph 34 in FIG. 3 will be determined practically, wherein the associated layouts of circuit blocks 12A and 12B is known by those skilled the art without need to be illustrated in the attached graph 34. After circuit layout design, the occupied square measure of each circuit block in circuit 10 and the geometric structure of the wire L1 to L4 have been determined. In order to practice this step in operation, CAD software could be applied to achieve the functional demand for automatic localization and APR, auto placement and routing.
Step 106: Parameters Determination. After circuit layout design in step 104, mutual electric coupling parameters between each wire such as resistance distributed in the circuit and capacity of mutual coupling equivalent capacitors between wires will be calculated according to the layout geometric structure. In wafer manufacturing processing, a square measure unit of each conductive polysilicon, and conductive layer is provided with a certain distributed resistance. After determining the wire layer and geometric structure, distributed resistance of each wire could be calculated. Similarly, the equivalent capacitance of each wire is related to the geometric distance of each wire, which could be calculated in this step. In order to practice this step in operation, resistor and capacitor analysis software, such as STAR_RC, can be applied.
Step 108: Coupling Nets Determination. Parameters determined in step 106 would be applied to make up a coupling net, which is needed for cross-talk analysis. Parameters such as distributed resistance, and mutual coupling capacitance between each wire in circuit 10 shall be determined in order to consider cross-talk effects between wires. After step 106, associated parameters could be determined. As illustrated in an attached graph 38 in FIG. 3, parameters about distributed resistance and mutual coupling equivalent capacitance of the wire L1 to L4 have been determined, and wires in the circuit 10 have been organized to make up a coupling net having resistors and capacitors. After making up the coupling net, mutual electric coupling effects between each wire have to be further analyzed. During a practical operation, this step can be done in step 106 by applying software resistor and capacitor analysis software. Generally, after analysis in step 106 and 108 with the aid of resistor and capacitor analysis software, a plurality of wires with critical mutual electric coupling effects among wires in circuit 10 can be determined and listed. In a more complex circuit, such as one of an application chip, there may be thousands of inter-connected wires between each circuit block, resistor and capacitor analysis software can list a plurality of wires with most critical mutual electric coupling effects just as the circuit designer wishes; for example, the most critical one thousand wires.
Step 110: Cross-Talk Analysis, which could be called SI, signal integrity, analysis Cross-talk effects between wires to signals transmitted in them can be determined according to the coupling net determined in step 108. In prior art, it is the most pessimistic condition being taken into accounts in cross-talk analysis. As illustrated in FIG. 2B, it will be considered in conventional cross-talk analysis that two single reverse transmitted at the same time in the wires L1 and L2 compensate each other completely, which make the delay time of signal transmitted in the wire L1 longest. Alternatively, as illustrated in FIG. 2A, which frequent transitions in both L1 and L2 result in the most critical interruption to signal transmitted in L1. Additionally, there is a potential transition from low to high just in both L1 and L2 such that the mutual coupling influence in the wire L1 is so large so as to have a highest potential in L1. In other words, in a conventional pessimistic cross-talk analysis, each transmitted signal will be considered whether or not generating the most critical cross-talk influences. In a practical operation of this step, signal analysis application software, such as MDC13SI, can be applied. As mentioned in step 108, after applying resistor and capacitor analysis software to list a plurality of wires having most critical mutual electric coupling effects, signal analysis application software can be applied to analyze influences of cross-talk of these plural wires. Usually, after analysis in this step, influences of cross-talk to each wire in circuit 10 can be listed for comparison so that the circuit designer is capable of telling which wires in circuit 10 are most intended to be influenced by cross-talk and what the influences are. The circuit designer can rearrange circuit layout according to the analytic result, and go back to step 104 to reduce cross-talk effects of such wires.
Though it is a strictly conservative standard to analyze cross-talk effects of each wire in step 110, to some of wires during a practical operation of circuit 10, the pessimistic condition will not occur. For example, in step 110 the wire L1 is analyzed to be easily influenced by cross L2 such that a frequent potential transition occurs in L2 to influence signal L1 by mutual electric coupling. However, during a practical operation of circuit 10, there may be no frequent transition in L2 because only signals with low frequency or direct current would be transmitted in L2. The transition frequency in unit time is much lower in L2 than L1. In such a condition, the rate in which L2 happens to have mutual compensation or addition coupling in pessimistic condition is very low because frequency differences between the two wires is so large that it is not easy for appearance of transitions synchronization. Cross-talk effects of practical operation of circuit 10 are not as critical as the result analyzed in step 110. It is the coupling net determined in step 108 being taken into accounts to do pessimistic analysis in step 110. The coupling net having only parameters information about coupling capacitance and distributed resistance cannot represent how circuit 10 operates and what kinds of signals are transmitted in each wire. Therefore, in order to get the pessimistic condition that signals happen to compensate or add each other in each wire, an analytic result with stricter standard shall be considered.
To each wire in circuit 10, if during a practical operation of the circuit the analytic pessimistic condition is highly different from real conditions, a cross-talk analysis result will mislead the circuit designer such that the circuit designer could not modify the circuit design correctly. For example, if the cross-talk analysis in step 110 represents that the wire L1 will be influenced seriously by cross-talk of the wire L2, the circuit designer has to return to step 104 from step 110 to redesign circuit layout of L1. However, during a practical operation of the circuit 10, rate of occurrence of the most pessimistic condition that signal transmitted in L1 and L2 synchronized is very rare. In such condition, too serious cross-talk analysis causes an unnecessary layout redesign. Besides the unnecessary waste of time, in modern highly integrated electric circuit design, each element usually interrupts each other, which is called trade-off. Some elements might be compromised in order to redesign the circuit. For example, it may result in signal deterioration while increasing a wire length. Some compromises are unnecessary. Therefore, ignoring signals transmitted during a practical operation of a circuit and strictly analyzing the cross-talk in pessimistic condition may result in unnecessary waste and a compromising circuit design.